1. Field of the Invention
The invention relates to the fabrication of polycrystalline silicon members for MOS circuits, or the like.
2. Prior Art
In the fabrication of integrated circuits, particularly metal-oxide-semiconductor (MOS) silicon gate devices there is a requirement for forming narrow polycrystalline silicon members such as gates for field-effect transistors, interconnecting lines, and others. Narrower silicon structures permit higher density fabrication and in the case of silicon gate field-effect transistors provide improved performance. By way of example, with current high production processes, silicon gates are typically 6 microns wide.
A major factor preventing a substantial reducing in gate widths (or the dimensions of other polycrystalline silicon members) is the tolerances inherent in current production masks. The shifting of the critical dimensions from a mask to the final member (such as by etching) also adds to the masking tolerances, however to a lesser extent particularly where selective etchants are employed. While more expensive fabrication techniques are known (such as electron beam photolithography) typical tolerances (masking and etching) for high production fabrication of silicon members are .+-.0.7 to .+-.1.0 microns, with the masking tolerance accounting for approximately.+-. 0.5 microns of this total. Thus, reliance on a mask for a critical dimension severely limits the fabrication of narrow members, that is, members less than a few microns.
The disclosed process does not use a mask to define critical dimensions. Rather the edge of a masking member is employed to form a gap or line opening. The critical dimensions, however, are controlled by a diffusion step. Thus, the resultant silicon structure is independent of the masking tolerances.